vishay siliconix si8441db document number: 74668 s-82119-rev. c, 08-sep-08 www.vishay.com 1 p-channel 20-v (d-s) mosfet features ? trenchfet ? power mosfet applications ? low threshold load switch for portable devices - low power consumption - increased battery life product summary v ds (v) r ds(on) ( ) i d (a) e q g (typ.) - 20 0.080 at v gs = - 4.5 v - 10.5 7.7 nc 0.102 at v gs = - 2.5 v - 9.3 0.128 at v gs = - 1.8 v - 3.5 0.198 at v gs = - 1.5 v - 2.5 0.600 at v gs = - 1.2 v - 0.5 micro foot device markin g : 8 441 xxx = date/lot tracea b ility code orderin g information: si 8 441db-t2-e1 (lead (p b )-free) dd ss sg 1 2 6 3 5 4 b u mp side v ie w 8 441 xxx backside v ie w s g d p-channel mosfet notes: a. surface mounted on 1" x 1" fr4 board. b. t = 10 s. c. refer to ipc/jedec (j-std- 020c), no manual or hand soldering. d. in this document, any reference to case represents t he body of the micro foot device and foot is the bump. e. based on t c = 25 c. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds - 20 v gate-source voltage v gs 5 continuous drain current (t j = 150 c) t c = 25 c i d - 10.5 a t c = 70 c - 8.4 t a = 25 c - 4.8 a, b t a = 70 c - 3.9 a, b pulsed drain current i dm - 15 continuous source-drain diode current t c = 25 c i s - 10.8 t a = 25 c - 2.3 a, b maximum power dissipation t c = 25 c p d 13 w t c = 70 c 8.4 t a = 25 c 2.77 a, b t a = 70 c 1.77 a, b operating junction and storage temperature range t j , t stg - 55 to 150 c package reflow conditions c ir/convection 260 rohs compliant
www.vishay.com 2 document number: 74668 s-82119-rev. c, 08-sep-08 vishay siliconix si8441db notes: a. surface mounted on 1" x 1" fr4 board. b. maximum under steady state conditions is 85 c/w. c. case is defined as top surface of the package. thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a, b r thja 37 45 c/w maximum junction-to-case (drain) steady state r thjc 79.5 specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 20 v v ds temperature coefficient v ds /t j i d = - 250 a - 20 mv/c v gs(th) temperature coefficient v gs(th) /t j 2.2 gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 0.35 - 0.7 v gate-source leakage i gss v ds = 0 v, v gs = 5 v 100 na zero gate voltage drain current i dss v ds = - 20 v, v gs = 0 v - 1 a v ds = - 20 v, v gs = 0 v, t j = 70 c - 10 on-state drain current a i d(on) v ds - 5 v, v gs = - 4.5 v - 5 a drain-source on-state resistance a r ds(on) v gs = - 4.5 v, i d = - 1 a 0.066 0.080 v gs = - 2.5 v, i d = - 1 a 0.085 0.102 v gs = - 1.8 v, i d = - 1 a 0.105 0.128 v gs = - 1.5 v, i d = - 1 a 0.145 0.198 v gs = - 1.2 v, i d = - 0.5 a 0.200 0.600 forward transconductance a g fs v ds = - 10 v, i d = - 1 a 7s dynamic b input capacitance c iss v ds = - 10 v, v gs = 0 v, f = 1 mhz 600 pf output capacitance c oss 130 reverse transfer capacitance c rss 70 total gate charge q g v ds = - 10 v, v gs = - 5 v, i d = - 1 a 8.5 13 nc v ds = - 10 v, v gs = - 4.5 v, i d = 1 a 7.7 12 gate-source charge q gs 0.85 gate-drain charge q gd 1.6 gate resistance r g v gs = - 0.1 v, f = 1 mhz 6.2 tu r n - o n d e l ay t i m e t d(on) v dd = - 10 v, r l = 10 i d ? - 1 a, v gen = - 4.5 v, r g = 1 15 25 ns rise time t r 30 45 turn-off delay time t d(off) 35 55 fall time t f 10 15
document number: 74668 s-82119-rev. c, 08-sep-08 www.vishay.com 3 vishay siliconix si8441db notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not subject to production testing. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c - 10.5 a pulse diode forward current i sm - 15 body diode voltage v sd i s = - 1 a, v gs = 0 v - 0.7 - 1.2 v body diode reverse recovery time t rr i f = - 1 a, di/dt = 100 a/s, t j = 25 c 20 40 ns body diode reverse recovery charge q rr 715nc reverse recovery fall time t a 11 ns reverse recovery rise time t b 9
www.vishay.com 4 document number: 74668 s-82119-rev. c, 08-sep-08 vishay siliconix si8441db typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current and gate voltage gate charge v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d 0 3 6 9 12 15 0 0.5 1.0 1.5 2.0 2.5 3.0 v gs = 4.5 thr u 2.5 v v gs =1 v v gs =1.5 v v gs =2 v i d - drain c u rrent (a) - on-resistance ( w ) r ds(on) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 3 6 9 12 15 v gs =2.5 v v gs =4.5 v v gs =1.5 v v gs =1. 8v q g - total gate charge (nc) - gate-to-so u rce v oltage ( v ) v gs 0 1 2 3 4 5 0246 8 10 i d =1a v ds =10 v v ds =16 v transfer characteristics capacitance on-resistance vs. junction temperature v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (a) i d 0 1 2 3 4 5 00.51.01.52.0 t c = 25 c t c = - 55 c t c = 125 c v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) 0 200 400 600 8 00 1000 04 8 12 16 20 c rss c oss c iss t j - j u nction temperat u re (c) 0.6 0. 8 1.0 1.2 1.4 1.6 - 50 - 25 0 25 50 75 100 125 150 r ds(on) - on-resistance ( n ormalized) i d = 1 a v gs = 4.5 v , 2.5 v , 1. 8 v v gs = 1.5 v
document number: 74668 s-82119-rev. c, 08-sep-08 www.vishay.com 5 vishay siliconix si8441db typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 t j = 150 c 10 v sd - source-to-drain voltage (v) - source current (a) i s 1 t j = 25 c 100 0.2 0.3 0.4 0.5 0.6 0.7 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a ( v ) v gs(th) t j - temperat u re (c) on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient v gs - gate-to-so u rce v oltage ( v ) - on-resistance ( w ) r ds(on) 0.05 0.10 0.15 0.20 0.25 012345 i d =1a 125 c 25 c 0 5 10 15 20 25 30 po w er ( w ) p u lse (s) 10 1000 0.1 0.01 0.001 100 1 safe operating area, junction-to-ambient 0.1 1 10 100 - drain c u rrent (a) i d v ds - drain-to-so u rce v oltage ( v ) * v gs > minim u m v gs at w hich r ds(on) is specified 100 1 0.01 10 1ms 0.1 limited b yr ds(on) * t c = 25 c single p u lse 10 ms 100 ms 1s,10s dc 100 s b v dss limited
www.vishay.com 6 document number: 74668 s-82119-rev. c, 08-sep-08 vishay siliconix si8441db typical characteristics 25 c, unless otherwise noted * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the current rating, when this rating falls below the package limit. current derating* i d - drain c u rrent (a) t c - case temperat u re (c) 0 2 4 6 8 10 12 0 25 50 75 100 125 150 power derating 0 3 6 9 12 15 25 50 75 100 125 150 t c - case temperature (c) power dissipation (w)
document number: 74668 s-82119-rev. c, 08-sep-08 www.vishay.com 7 vishay siliconix si8441db typical characteristics 25 c, unless otherwise noted normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 0 0 0 1 0 1 1 10 -1 10 -4 100 0.2 0.1 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 t 1 t 2 n otes: p dm 1. d u ty cycle, d = 2. per unit base = r thja = 65 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 4. s u rface mo u nted d u ty cycle = 0.5 single p u lse 0.02 0.05 normalized thermal transient impedance, junction-to-case 10 -3 10 -2 10 -1 10 -4 1 0.1 0.2 0.1 d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 0.02 0.05 single p u lse
www.vishay.com 8 document number: 74668 s-82119-rev. c, 08-sep-08 vishay siliconix si8441db package outline micro foot: 6-bump (2 x 3, 0.5 mm pitch) notes (unless otherwise specified): 1. all dimensions are in millimeters. 2. six (6) solder bumps are lead (pb)-fr ee 95.5sn, 3.8ag, 0.7cu with diameter ? 0.30 to 0.32 mm. 3. backside surface is coated with a ti/ni/ag layer. 4. non-solder mask defined copper landing pad. 5. is location of pin 1. notes: a. use millimeters as the primary measurement. vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?74668. e e e s s d d s g a b c 1 2 recommended land e e mark on backside of die s xxx 8 441 a a1 a2 s d e s s e 6 x ? 0.24 to 0.26 n ote 3 solder mask ~ ? 0.25 b u mp n ote 2 6 x ? b dim. millimeters a inches min. nom. max. min. nom. max. a 0.510 0.575 0.590 0.0201 0.0224 0.0232 a 1 0.220 0.250 0.280 0.0087 0.0098 0.0110 a 2 0.290 0.300 0.310 0.0114 0.0118 0.0122 b 0.300 0.310 0.320 0.0118 0.0122 0.0126 e 0.500 0.0197 s 0.230 0.250 0.270 0.0090 0.0098 0.0106 d 0.920 0.960 1.000 0.0362 0.0378 0.0394 e 1.420 1.460 1.500 0.0559 0.0575 0.0591
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